1. Field of the Invention
The present invention relates to a sensing circuit, and more particularly, to a sense amplifier for a memory device.
2. Background of the Related Art
FIG. 1 illustrates a sense amplifier according to the background art, which includes a pair of pull-down amplifiers 10 and 11, a precharge unit 12 and an equalizing unit 13. Each of the pull-down amplifiers 10 and 11 has a pair of input terminals and a pair of output terminals. The output terminals of the pull-down amplifiers 10 and 11 are respectively connected with data lines DL0, DL0b and DL1, DL1b. The precharge unit 12 and the equalizing unit 13 are connected with the data lines DL0, DL0b and DL1, DL1b.
FIG. 2 is a detailed circuit view of the sense amplifier illustrated in FIG. 1. The pull-down amplifiers 10 and 11 are amplifiers for sensing a voltage on an output terminal which is lower than a precharge voltage PV. The pull-down amplifier 10 is enabled by a sense amplifier enable signal SAEN to sense data provided from a corresponding memory cell of the memory device on input terminals IN0, IN0b of the NMOS transistors NM1, NM2, and the amplifier 10 outputs the sensed data to the data lines DL0, DL0b. The pull-down amplifier 11 is enabled by the sense amplifier enable signal SAEN to sense data from a corresponding memory cell of a memory device on input terminals IN1, IN1b applied to the NMOS transistors NM4, NM5, and the amplifier 11 outputs the data to the data lines DL1, DL1b.
Pursuant to an equalizing signal DLEQ, the precharge unit 12 precharges the data lines DL0, DL0b and DL1, DL1b to the precharge voltage PV provided from an external source. Pursuant to the equalizing signal DLEQ, the equalizing unit 13 electrically connects the data lines DL0, DL0b and DL1, DL1b, respectively.
The operation of the FIG. 1 sense amplifier is described with reference to FIGS. 1, 2, 3A and 3B. In a precharge period, the PMOS transistors PM1-PM4 of the precharge unit 12 and the PMOS transistors PM5-PM6 of the equalizing unit 13 are turned on in accordance with the equalizing signal DLEQ of a low level. The data lines DL0, DL0b and DL1, DL1b are electrically connected by the equalizing unit 13 and the precharge unit 12 at the same time. The precharge unit 12 precharges all data lines to the precharge voltage PV. As a result, the data lines DL0, DL0b and DL1, DL1b have a potential of the precharge voltage PV. When the precharging operation is completed, the precharge unit 12 and the equalizing unit 13 are disabled by the equalization signal (DLEQ) of a high level.
In a sensing period, the pull-down amplifiers 10, 11 are enabled by the sense amplifier enable signal SAEN. The pull-down amplifier 10 senses the data read from the memory cell on input terminals IN0, IN0b, which are applied to the gates of the NMOS transistors NM1, NM2. The pull-down amplifier 11 senses the data read from the memory cell on input terminals IN1, IN1b, which are applied to the gates of NMOS transistors NM4, NM5. The amplifier 10 amplifies the voltage difference at the input terminals IN0, IN0b such that a voltage difference of PV-Vss exists between the data lines DL0, DL0b, as shown in FIG. 3A. Similarly, the amplifier 11 amplifies the voltage difference at the input terminals IN1, IN1b such that a voltage difference of PV-Vss exists between the data lines DL1, DL1b, as shown in FIG. 3B.
Thereafter, the precharge unit 12 and equalizing unit 13 are turned on to perform a precharging operation such that all data lines DL0, DL0b, and DL1, DL1b are recharged to the precharge voltage PV. The precharging operation and the sensing operation are repeatedly performed, and the data read from the memory cell are provided through the data lines DL0, DL0b and DL1, DL1b after being amplified in the pull-down amplifiers 10, 11. Accordingly, the reading operation from the memory cells is performed.
However, the above-described sense amplifier has various disadvantages. One disadvantage is the large electric power consumption. That is, during the sensing operation, one of the data lines DL0, DL0b and one of the data lines DL1, DL1b decreases to PV-.DELTA.V and then are precharged with the precharge voltage PV again during the subsequent precharge operation, At this time, the current flow is generated. As a result, electric current is continuously consumed in both the precharge operation and the sensing operation.